Today's fiber optic based networks use transceivers or other optical subsystems at the interface between electronic systems and the optical fiber communications link or network. A transceiver is generally used to convert between electrical data and optical signals that are transmitted via optical fibers. There are many applications for transceivers ranging from fiber to the home, to data centers to telecommunications, to long haul and high-performance communications and computing. Often, the optical transceiver, responsible for receiving and transmitting optical data from the fiber, is built in a pluggable form. Pluggable transceivers are hot-swappable, input/output transceivers used in data communication and telecommunications networks. These pluggable transceivers interface between communication devices like switches, routers and fiber optic cables, and perform conversions between optical and electrical signals and standardized form factors have been developed as a result of transceiver multisource agreements. Standardized form factors include XFP, QSFP+, SFP, and CFP packages, that includes electrical, optical and mechanical, or power dissipation/usage as well other factors that enable a module to be purchased from different vendors to meet the needs of customers using these pluggables. Standardized pluggable transceivers enable modularity and field replacement functions like hot swapping in addition to the cost and size benefits of a standardized form factor. The use of a standardized form factor allows an optical pluggable transceivers to be connected to fiber transmission systems using any given compatible port of the electronic system.
The performance of the transceiver, as well as its cost, is tied to a particular application. Today, most transceivers are manufactured in a pluggable form factor that can be installed and removed from a linecard or system without turning on and off the system power and allow the transceiver to be inserted and removed from a card cage slot. These pluggables may also be installed internal to the system or on the linecard directly to increase density, or the internal components of the pluggable integrated directly onto the circuitry of the linecard, daughter card or some other module that is used for communications inside the switching or routing equipment. The transceiver interfaces to a host (or client) through several different data processing chips that conform data from the host to the transmission medium and vice versa. In today's transceivers and pluggable transceivers, a microprocessor or microcontroller is used as the central element to run the transceiver module, control the data and other signals as well as monitor the health and behavior of a transceiver. Depending on the choice of cost, size and power dissipation, for smaller form factors the signal processing chips are placed on the host, whereas on larger form factors they can placed inside the transceiver.
Known prior art signal processing and transceiver controls rely on various components that perform electro-optical interfacing and functions such as serialization/deserialization (SerDes), which conforms lower bit rate parallel data to higher bit rate parallel or serial data and vice versa and a PHY which contains functions such as framing, and will insert data to be transmitted into transmission frames, e.g. Ethernet or SONET.
The PHY is a chip or set of chips used to adapt data traffic from the electronic host to the transport medium and vice versa by applying various data and signal processing techniques including but not limited to encoding/decoding, scrambling/descrambling, time alignment for asynchronous data protocols, receiver rate matching for clock frequency compensation and a gear-box function between data and clock traces on a circuit card and the data and clock rates inside the transceiver. The PHY also encodes and decodes data to ensure 50/50% marks and spaces in the data stream and in the process eliminates long sequences of Marks and Spaces, using for instance 8B/10B encoding where each 8 bit sequence is replaced with a 10 bit sequence. It also performs mapping functions, mapping a data stream at one bit rate to another bit rate.
Additionally, a Forward Error Correction (FEC) chip may be used, depending on the implementation, in some known prior art devices. The FEC chip adds another framing and encoding layer to the data to increase resilience to transmission impairments allowing for errors induced to be detected and corrected. Those skilled in the art will be familiar with the various designs and will know that the chips incorporating these functions can be in the transceiver or on the host board depending on the standard employed. It will also be understood by those skilled in the art, that the chips incorporating these functions will only process the IO data and will have no ability to otherwise control transceiver behavior, e.g. laser output power, tunable laser wavelength or temperature.
In presently known transceivers, a microcontroller or microprocessor is used to control the behavior and monitor the health of the transceiver. The microcontroller is a sequential execution machine and if multiple processor cores are used, some level of parallelism may be employed, but the execution is mostly sequential and software driven. Software is run on these chips to execute the required functions and the speed and efficiency as well as the reliability and adaptability of the control is dependent on the performance of the microcontroller/microprocessor and the code implemented. The ability to update or reconfigure the transceiver, or debug its functions as well as the performance like throughput and latency, are often limited by the use of software to handle these functions. The microcontroller/microprocessor is used in conjunction with digital to analog converters (DACs) and analog to digital converters (ADCs). A microcontroller or microprocessor, hereafter referred to as processing units, is a central processing unit (CPU) that contains a number of different peripheral modules to make it a stand-alone functional unit capable of facilitating transceiver monitoring and control. These functional units may include volatile and non-volatile memory, clock, oscillator, serial port, I2C/MDIO/SPI communications ports and Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC). The DAC and ADC functions can be integrated into special purpose integrated circuits called application specific integrated circuits (ASICs) that are interfaced to the processing units.
Those skilled in the art are familiar with the various designs and electronic circuitry that can be used to combine the different functions, including a SerDes (used to multiplex data from lower to higher data rates and visa versa from higher to lower data rates) and PHY, used with no FEC, or another combination where a SerDes is used with both PHY and FEC. In these cases the PHY can use any combination of internal functions to process the data stream, for instance perform both 8B/10B encoding and subsequent 64B/65B encoding for transmission over SONET. The different bit rate and signal processing function combinations are known to those of skill in the art. An example of a known data synchronization device is described in U.S. Pat. No. 7,457,389, and an example of known interconnections techniques, used in a physical interface modules, is described in US 2010/022907.
However, there are several disadvantages of known technology in this area. For example, today's SerDes, PHYs and FECs are typically separate modules with limited reconfiguration options outside of standards. Thus, a lot of the required functions are performed over several different integrated circuits, losing the flexibility of integrated timing and clock control, resulting in more complex circuitry. Also, as complex functions are implemented in hardware, future transmission systems will have to use the same generic functions to be able to use the same physical SerDes/PHY/FEC parts. This imposes limitations on how future standards are or will be defined. In contrast, networks are engineered, with increasing frequency, not towards standards, but towards requirements that are non-standard and specific to the network. Custom traffic and functional engineering is becoming more and more common. Such non-standard networks typically rely on specialty hardware designed to perform functions not available with current standardized hardware, or have to conform to specifications in standard hardware. In today's MAC and PHY solutions, the processing is controlled by changing register values and thus turning on or off certain hardware implemented functions, e.g. 8B/10B encoding and decoding, in the data path. Thus, the number of functions implemented is limited in both number and degree of flexibility. This means, for example, that a given part can only cover a limited amount of market segments (e.g. SONET and SDH) and that a different part is required for another market segment (e.g., 10 GigE). The result is that a large number of different parts are required to cover the market, thus increasing development, production and operational costs.
The other limitation is related to the use of a sequential processing machine like a microprocessor or microcontroller as the main element in the transceiver. The use of sequential machines to control the many functions described above, in conjunction with auxiliary ASICs, memory elements, and firmware processing devices like FPGAs used as auxiliary input/output devices, severely limits the performance of these systems and approaches, as well as the manufacturability, the cost, the ability to debug and improve operation by installation of updated operational software.
Another limitation is the sequential nature of a microprocessor or microcontroller centric design requires functions and communication to the various data and control functions and circuits to be built out of monolithic code that must be updated as a whole rather than a more efficient hardware implemented architecture, like that of the present invention, that allows multiple individual processes, that can be increased and added without affecting existing processes, to run the various functions of the transceiver in hardware, using concurrent or serial processes, independent or dependent processes, in hardware gate level defined circuits that are programmed in firmware, using software external to the system for programming stages only where real time operation is not based on software.
Another limitation of prior state of the art, is the manner in which the control and data portions of transceivers are connected to the optical to electronic conversion stages, and the various components needed to control the many functions and interact with the data. Today the optical, opto-electronic and in particular photonic integrated circuits (PICs) that communicate between electronic data and the fiber optic network or transmission system are moving towards increasing complexity, with more functions required to be controlled and monitored, including optical power, modulation, transmission and receiving parameters, and in some applications wavelength, temperature and other aspects. Today's optical chips and PICs can vary widely their design and implementation in order to match the cost and reliability of this interface for the desired application. Therefore the design of the electronics that interface between these chips and the electronics described above and the code and functions run on the microprocessors or microcontrollers can vary widely, as well as the circuitry designed into the interfacing ASICs, DACs and ADCs. This wide variability in hardware and control leads to inefficiencies in design across different optical and PICs as well as applications as well as increased cost for ASICs and changes in hardware and software designs as the application dictates different operation performance from the optics/PICs as well as control functions in the processors and the interfacing electronic circuitry.
Accordingly, there is a need for improved methods and apparatus to overcome the above-described limitations in the area of optical devices and subassemblies, including fiber optic transceivers, optical pluggables, board mounted transceivers and other optical communications devices that communicate data between an electronic system and an optical fiber communications system or network.